1. Field of the Invention
This invention generally relates to a floating-point processor and more particularly to a floating-point processor which can round a mantissa in a floating-point representation of data representing the result of a floating-point arithmetic operation at a high speed.
2. Description of the Related Art
A conventional circuit for performing addition and subtraction of floating-point data has a configuration as illustrated in, for example, a schematic block diagram of FIG. 8. In this figure, reference characters Xe and Xf designate data (hereunder referred to as exponent part data) representing an exponent part (i.e., a characteristic) of input data X and data (hereunder referred to as fixed-point part data) representing a fixed-point part (i.e., a mantissa) of the input data X, respectively; Ye and Yf exponent part data and fixed-point part data corresponding to input data Y, respectively; 801 an exponent comparing circuit for comparing the exponent part data Xe and Ye of input data X and Y; 802, 803 and 804 selection circuits; 805 a shift circuit; 806 an adder-subtracter circuit; 807 a rounding circuit; 808 a normalization circuit; and Ze and Zf exponent part data and fixed-point part data corresponding to output data Z, respectively.
Hereinafter, an operation of the circuit of FIG. 8 will be described. First, the exponent part data Xe corresponding to the input data X is compared with that Ye corresponding to the input data Y by the comparing circuit 801. Then, the fixed-point part data corresponding to the input data X or Y, the exponent part of which is smaller than that of the other input data, is inputted to the shift circuit 805. Further, the selection circuits 802, 803 and 804 are controlled such that the fixed-point part data corresponding to the input data Y or X, the exponent part of which is greater than that of the other input data, is inputted to the adder-subtracter circuit 806 and the exponent part data corresponding to the input data having the greater exponent part is inputted to the normalization circuit 808. Moreover, at that time, the difference between the exponent parts of the input data X and Y is inputted to the shift circuit 805 as a shift amount. Next, the fixed-point part data inputted to the shift circuit 805 is shifted right by the shift amount (i.e., the difference between the exponent parts of the input data). Thereby, the fixed-point part data corresponding to the input data having the smaller exponent part is aligned with the fixed-point part data corresponding to the input data having the greater exponent part. At that time, among digits which are forced out to the right by the shift and have orders lower than the least significant digit of the resultant data of the shift, the highest order one is employed as a guard digit; the next higher order one as a round digit; and a logical sum of all of the remaining ones as a sticky digit. Thus, information on the guard digit, the round digit and the sticky digit is stored for a rounding operation. Then, in the adder-subtracter circuit 806, the aligned two pieces of the fixed-point part data are added in case where an operation to be performed on the fixed-point part data is an addition. In contrast, a subtraction of the aligned two pieces of the fixed-point parts is performed therein in case where the operation to be performed on the fixed-point part data is an subtraction. Further, the result of the addition or subtraction is outputted to the rounding circuit 807. Incidentally, based on signs of the input data, the relation in magnitude between the two pieces of the exponent part data corresponding to the input data and which of an addition and a subtraction an operation to be performed on the exponent part data is, it is determined which of an addition and a subtraction the operation to be performed on the fixed-point part data is. If the resultant data of the adder-subtracter circuit 806 is negative, data representing a two's complement thereof is generated in the rounding circuit 807 for obtaining the absolute value thereof. Conversely, if positive, the result of the operation on the fixed-point parts is rounded to a predetermined digit and further the result of the rounding is outputted to the normalization circuit 808. The rounding circuit 806 is composed of adders and adds a carry (hereunder sometimes referred to as a rounding carry), which is caused by a rounding, to a predetermined digit of data representing the result of the operation. Next, the fixed-point part of the data inputted to the normalization circuit 808 is shifted right or left therein for the purpose of normalization of the data inputted thereto. If right-shifted, a corresponding shift amount is added to the exponent part data corresponding to the data inputted to the normalization circuit 808. In contrast, if left-shifted, the corresponding shift amount is subtracted from the exponent part data. Then, the operation is performed on the exponent part data. Subsequently, the exponent part data Ze and the fixed-point data Zf corresponding to the result of the addition are outputted. Thus, the operation of the floating-point data is completed.
Next, a conventional circuit for performing a multiplication of floating-point data has a configuration as illustrated in, for example, a schematic block diagram of FIG. 9. In this figure, reference characters Xe and Xf designate exponent part data and fixed-point part data corresponding to the input data X, respectively; Ye and Yf exponent part data and fixed-point part data corresponding to input data Y, respectively; 901 an exponential operation circuit; 902 a fixed-point part multiplier; 903 an adder circuit; 904 a rounding circuit; 905 a normalization circuit; and Ze and Zf exponent part data and fixed-point part data corresponding to output data Z, respectively. Incidentally, reference numeral 900 designates a fixed-point part calculating portion which includes the adder circuit 903 and the rounding circuit 904.
Hereinafter, an operation of the circuit of FIG. 9 will be described. First, the exponent part data Xe and Ye are inputted to the exponential operation circuit 901 whereupon an intermediate exponential operation is performed. Practically, an operation (Xe+Ye-Bi) is performed and the result of this operation is outputted to the normalization circuit 905. Here, Bi represents a bias of an exponent part in a floating-point representation. In case of employing a single precision format of IEEE 754 floating-point standard, Bi=127. Further, in case of employing a double precision format, Bi=1023.
Simultaneously with this operation performed on the exponent part data, the fixed-point part data Xf and Yf are inputted to the fixed-point part multiplier 902 whereupon a plurality of partial products are generated and then the generated partial products are serially added and finally two partial products A and B are generated and outputted. Subsequently, the outputs A and B of the fixed-point part multiplier 902 are added in the adder circuit 903. The result of the addition is outputted from the circuit 903 to the rounding circuit 904. The rounding circuit 904 rounds the result of the operation inputted from the circuit 903 to a predetermined digit and outputs the result of the rounding to the normalization circuit 905. This rounding circuit is composed of adder circuits and adds a rounding carry to a predetermined digit of the result of the operation. Finally, an alignment of the fixed-point part data and a correction of the exponent part data are effected in the normalization circuit 905, and the exponent part data Ze and the fixed-point part data Zf of the result of the multiplication is outputted therefrom. Thus, the multiplication operation is completed.
In case of the above described floating-point adder, the rounding operation is started in the rounding circuit after the operation on the fixed-point part data is completed in the adder-subtracter circuit. If the result of the operation effected in the adder-subtracter circuit is negative, the rounding circuit generates the two's complement of the data representing the result of the operation for obtaining the absolute value thereof. In contrast, if positive, the rounding circuit rounds the result of the operation performed on the fixed-point part data to the predetermined digit. It cannot be determined until the result of the operation effected in the adder-subtracter circuit is obtained whether or not the result of the operation is negative. Further, the generation of the two's complement is effected by performing an logical inversion of each digit of the result of the operation and then adding 1 to the converted result of the operation. Incidentally, when rounding the result of the operation performed on the fixed-point part data, there are two digit positions to which the result of the operation is rounded in case where an addition of the fixed-point part data is effected. This is because there are two cases, namely, a case in which an overflow occurs and another case in which no overflow does not occur when effecting the addition of the fixed-point part data. Further, the number of all digits of the fixed-point part data is determined depending on the format of the data. Therefore, for the alignment of the fixed-point parts, a digit position, to which the result of the operation is rounded in case where an overflow occurs when effecting the addition of the fixed-point part data, should be higher by one digit position than another digit position to which the result of the operation is rounded in case where no overflow occurs. Similarly, when a subtraction is effected between the fixed-point part data, there are two cases, namely, a case where an underflow occurs and another case when no underflow occurs. Thus, there are two digit places, to which a rounding of the operation is rounded, corresponding to the two cases, respectively. However, it cannot be determined until the result of an operation is obtained whether an overflow or underflow occurs correspondingly to the operation. Thus, in case of the above described conventional floating-point adder, it cannot be determined until the result of an operation effected in the adder-subtracter circuit is obtained whether or not the result is negative and whether an overflow or underflow occurs. Therefore, the generation of the two's complement of the result of the operation, as well as the rounding operation, cannot be started until the result of the operation effected in the adder-subtracter circuit is obtained. Consequently, the above described conventional floating-point adder has drawbacks that the addition and subtraction and the rounding operation are time-consuming and that the configuration of the circuit becomes complex.
Further, in case of the above described conventional floating-point multiplier, the rounding operation of the rounding circuit is commenced after the partial products finally obtained by the adder circuit are added. When rounding the fixed-point part data, there are similarly two digit positions to which the fixed-point part data is rounded, in case of effecting the multiplication. This is because there are two cases, namely, a case in which an overflow occurs and another case in which no overflow does not occur when effecting the multiplication of the fixed-point part data. Therefore, similarly as in case of the conventional floating-point adder, it cannot be determined until the partial product are added whether or not an overflow occurs. Thus, in case of the above described conventional floating-point multiplier, the rounding operation cannot be started until the result of the addition of the partial products to be effected by the adder circuit is definitely determined. Consequently, the above described conventional floating-point multiplier has similar drawbacks that the addition of the partial products and the rounding of the result of the operation are time-consuming and that the configuration of the circuit becomes complex. The present invention is accomplished to eliminate the above stated drawbacks of the conventional floating-point processors.
It is, accordingly, an object of the present invention to provide a floating-point processor which includes an additional circuit added to an adder-subtracter circuit, thereby performing an arithmetic operation on fixed-point part data, a calculation of an absolute value of a result of the operation and a rounding of the result of the operation at a high speed with a simple configuration.
Further, it is another object of the present invention to provide a floating-point processor which includes an additional circuit added to an adder for adding two partial products finally obtained therein, thereby performing an arithmetic operation on fixed-point part data and a rounding of the result of the operation at a high speed with a simple configuration.